Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

TL;DR

This paper explores a two-layer silicon pixel detector design to identify cosmic muons impacting quantum processors, aiming to improve quantum error correction by mitigating radiation-induced errors.

Contribution

It introduces a conceptual design for a silicon pixel detector capable of operating at cryogenic temperatures to detect cosmic muons affecting quantum computing hardware.

Findings

Detector efficiency >50% at cryogenic temperatures

Deep-cryogenic operation feasible with proposed design

Potential for real-time muon tagging in quantum processors

Abstract

Recent studies in quantum computing have shown that quantum error correction with large numbers of physical qubits are limited by ionizing radiation from high-energy particles. Depending on the physical setup of the quantum processor, the contribution of muons from cosmic sources can constitute a significant fraction of these interactions. As most of these muons are difficult to stop, we perform a conceptual study of a two-layer silicon pixel detector to tag their hits on a solid-state quantum processor instead. With a typical dilution refrigerator geometry model, we find that efficiencies greater than 50% are most likely to be achieved if at least one of the layers is operated at the deep-cryogenic (<1 K) flanges of the refrigerator. Following this finding, we further propose a novel research program that could allow the development of silicon pixel detectors that are fast enough to provide input to quantum error correction algorithms, can operate at deep-cryogenic temperatures, and have very low power consumption.