Efficient Hardware Implementation of Constant Time Sampling for HQC

TL;DR

This paper presents a hardware-optimized implementation of a secure sampling algorithm for HQC, significantly reducing latency and resource usage on FPGA without compromising security against side-channel attacks.

Contribution

It introduces a cross layer optimization technique for the new sampling algorithm, enabling efficient FPGA implementation while maintaining security robustness.

Findings

Latency reduced by a factor of 24 compared to original algorithm

Resource usage significantly lower than previous implementations

Implementation validated on Xilinx Artix 7 FPGA

Abstract

HQC is one of the code-based finalists in the last round of the NIST post quantum cryptography standardization process. In this process, security and implementation efficiency are key metrics for the selection of the candidates. A critical compute kernel with respect to efficient hardware implementations and security in HQC is the sampling method used to derive random numbers. Due to its security criticality, recently an updated sampling algorithm was presented to increase its robustness against side-channel attacks. In this paper, we pursue a cross layer approach to optimize this new sampling algorithm to enable an efficient hardware implementation without comprising the original algorithmic security and side-channel attack robustness. We compare our cross layer based implementation to a direct hardware implementation of the original algorithm and to optimized implementations of the previous sampler version. All implementations are evaluated using the Xilinx Artix 7 FPGA. Our results show that our approach reduces the latency by a factor of 24 compared to the original algorithm and by a factor of 28 compared to the previously used sampler with significantly less resources.