A Ferroelectric Compute-in-Memory Annealer for Combinatorial Optimization Problems

TL;DR

This paper introduces a novel FeFET-based compute-in-memory annealer designed for efficiently solving combinatorial optimization problems by leveraging hardware-algorithm co-design, in-situ acceleration, and a new optimization algorithm.

Contribution

It presents a scalable, energy-efficient FeFET CiM annealer with a lossless compression technique and a multi-epoch simulated annealing algorithm, advancing hardware solutions for COPs.

Findings

Successfully solved graph coloring problem with chip prototypes

Achieved faster convergence and better solutions with MESA algorithm

Demonstrated hardware scalability and versatility for various COPs

Abstract

Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications, including logistical planning, resource allocation, chip design, drug explorations, and more. Due to their critical significance and the inability of conventional hardware in efficiently handling scaled COPs, there is a growing interest in developing computing hardware tailored specifically for COPs, including digital annealers, dynamical Ising machines, and quantum/photonic systems. However, significant hurdles still remain, such as the memory access issue, the system scalability and restricted applicability to certain types of COPs, and VLSI-incompatibility, respectively. Here, a ferroelectric field effect transistor (FeFET) based compute-in-memory (CiM) annealer is proposed. After converting COPs into quadratic unconstrained binary optimization (QUBO) formulations, a hardware-algorithm co-design is conducted, yielding an energy-efficient, versatile, and scalable hardware for COPs. To accelerate the core vector-matrix-vector (VMV) multiplication of QUBO formulations, a FeFET based CiM array is exploited, which can accelerate the intended operation in-situ due to its unique three-terminal structure. In particular, a lossless compression technique is proposed to prune typically sparse QUBO matrix to reduce hardware cost. Furthermore, a multi-epoch simulated annealing (MESA) algorithm is proposed to replace conventional simulated annealing for its faster convergence and better solution quality. The effectiveness of the proposed techniques is validated through the utilization of developed chip prototypes for successfully solving graph coloring problem, indicating great promise of FeFET CiM annealer in solving general COPs.