ONNX-to-Hardware Design Flow for the Generation of Adaptive Neural-Network Accelerators on FPGAs

TL;DR

This paper explores a new FPGA-based design flow for adaptive neural network accelerators, combining existing toolchains with approximate computing to enable lightweight, flexible, and energy-efficient NN inference at the edge.

Contribution

It introduces a novel approach that integrates adaptive toolchains with approximate computing for FPGA-based neural network acceleration.

Findings

Reviewed existing frameworks with streaming architecture

Proposed a combined approach for adaptivity and efficiency

Lays groundwork for lightweight edge NN inference

Abstract

Neural Networks (NN) provide a solid and reliable way of executing different types of applications, ranging from speech recognition to medical diagnosis, speeding up onerous and long workloads. The challenges involved in their implementation at the edge include providing diversity, flexibility, and sustainability. That implies, for instance, supporting evolving applications and algorithms energy-efficiently. Using hardware or software accelerators can deliver fast and efficient computation of the \acp{nn}, while flexibility can be exploited to support long-term adaptivity. Nonetheless, handcrafting an NN for a specific device, despite the possibility of leading to an optimal solution, takes time and experience, and that's why frameworks for hardware accelerators are being developed. This work-in-progress study focuses on exploring the possibility of combining the toolchain proposed by Ratto et al., which has the distinctive ability to favor adaptivity, with approximate computing. The goal will be to allow lightweight adaptable NN inference on FPGAs at the edge. Before that, the work presents a detailed review of established frameworks that adopt a similar streaming architecture for future comparison.