Platform-Aware FPGA System Architecture Generation based on MLIR

TL;DR

This paper introduces Olympus, an MLIR-based framework for automating the generation and optimization of platform-aware FPGA system architectures, reducing manual effort and increasing extensibility.

Contribution

It presents Olympus MLIR dialect and Olympus-opt passes for automated, reusable FPGA architecture design tailored to specific platform features.

Findings

Automates FPGA architecture generation with MLIR

Reduces manual platform-specific design effort

Enhances extensibility and reusability of FPGA design tools

Abstract

FPGA acceleration is becoming increasingly important to meet the performance demands of modern computing, particularly in big data or machine learning applications. As such, significant effort is being put into the optimization of the hardware accelerators. However, integrating accelerators into modern FPGA platforms, with key features such as high bandwidth memory (HBM), requires manual effort from a platform expert for every new application. We propose the Olympus multi-level intermediate representation (MLIR) dialect and Olympus-opt, a series of analysis and transformation passes on this dialect, for representing and optimizing platform aware system level FPGA architectures. By leveraging MLIR, our automation will be extensible and reusable both between many sources of input and many platform-specific back-ends.