The Importance of Worst-Case Memory Contention Analysis for Heterogeneous SoCs

TL;DR

This paper emphasizes the critical need for accurate worst-case memory contention analysis in heterogeneous SoCs, revealing that common assumptions can significantly underestimate interference, which varies by hardware architecture.

Contribution

It demonstrates that worst-case interference patterns are hardware-dependent and challenges the common synthetic workload assumptions used in prior analyses.

Findings

Worst-case interference can be underestimated by over 9x using synthetic workloads.

Memory interference patterns vary significantly across different hardware architectures.

Assumptions in interference estimation may lead to unsafe worst-case timing guarantees.

Abstract

Memory interference may heavily inflate task execution times in Heterogeneous Systems-on-Chips (HeSoCs). Knowing worst-case interference is consequently fundamental for supporting the correct execution of time-sensitive applications. In most of the literature, worst-case interference is assumed to be generated by, and therefore is estimated through read-intensive synthetic workloads with no caching. Yet these workloads do not always generate worst-case interference. This is the consequence of the general results reported in this work. By testing on multiple architectures, we determined that the highest interference generation traffic pattern is actually hardware dependant, and that making assumptions could lead to a severe underestimation of the worst-case (in our case, of more than 9x).