A Switch Architecture for Time-Triggered Transmission with Best-Effort Delivery

TL;DR

This paper introduces a novel switch architecture that combines time-triggered and best-effort transmission methods, significantly reducing latency and improving jitter control in real-time industrial networks.

Contribution

The paper proposes a synergistic switch architecture (SWA) that enables dynamic, opportunistic use of best-effort delivery to enhance time-triggered transmission performance.

Findings

SWA reduces end-to-end latency for TT frames.

SWA achieves controllable jitter in TT networks.

Implementation on FPGA demonstrates practical benefits.

Abstract

In Time-Triggered (TT) or time-sensitive networks, the transmission of a TT frame is required to be scheduled at a precise time instant for industrial distributed real-time control systems. Other (or {\em best-effort} (BE)) frames are forwarded in a BE manner. Under this scheduling strategy, the transmission of a TT frame must wait until its scheduled instant even if it could have been transmitted sooner. On the other hand, BE frames are transmitted whenever possible but may miss deadlines or may even be dropped due to congestion. As a result, TT transmission and BE delivery are incompatible with each other. To remedy this incompatibility, we propose a synergistic switch architecture (SWA) for TT transmission with BE delivery to dynamically improve the end-to-end (e2e) latency of TT frames by opportunistically exploiting BE delivery. Given a TT frame, the SWA generates and transmits a cloned copy with BE delivery. The first frame arriving at the receiver device is delivered with a configured jitter and the other copy ignored. So, the SWA achieves shorter latency and controllable jitter, the best of both worlds. We have implemented SWA using FPGAs in an industry-strength TT switches and used four test scenarios to demonstrate SWA's improvements of e2e latency and controllable jitter over the state-of-the-art TT transmission scheme.