Software Compartmentalization Trade-Offs with Hardware Capabilities

TL;DR

This paper explores hardware-assisted compartmentalization on the ARM Morello chip using CHERI, proposing two schemes with different trade-offs, demonstrating low engineering effort and comparable performance overheads to existing methods.

Contribution

It introduces two new CHERI-based compartmentalization schemes on Morello, analyzing their trade-offs in security, scalability, and performance, and implements them on a prototype OS.

Findings

Compartmentalization can be achieved with low engineering effort.

Performance overheads are comparable to existing intra-address space isolation methods.

Trade-offs exist between security, scalability, and engineering effort.

Abstract

Compartmentalization is a form of defensive software design in which an application is broken down into isolated but communicating components. Retrofitting compartmentalization into existing applications is often thought to be expensive from the engineering effort and performance overhead points of view. Still, recent years have seen proposals of compartmentalization methods with promises of low engineering efforts and reduced performance impact. ARM Morello combines a modern ARM processor with an implementation of Capability Hardware Enhanced RISC Instructions (CHERI) aiming to provide efficient and secure compartmentalization. Past works exploring CHERI-based compartmentalization were restricted to emulated/FPGA prototypes. In this paper, we explore possible compartmentalization schemes with CHERI on the Morello chip. We propose two approaches representing different trade-offs in terms of engineering effort, security, scalability, and performance impact. We describe and implement these approaches on a prototype OS running bare metal on the Morello chip, compartmentalize two popular applications, and investigate the performance overheads. Furthermore, we show that compartmentalization can be achieved with an engineering cost that can be quite low if one is willing to trade off on scalability and security, and that performance overheads are similar to other intra-address space isolation mechanisms.