Flip: Data-Centric Edge CGRA Accelerator

TL;DR

Flip is a data-centric CGRA accelerator that significantly improves graph processing performance by mapping vertices to processing elements and supporting dynamic data routing, achieving up to 36x speedup.

Contribution

It introduces a novel data-centric mode for CGRA architectures, enhancing their ability to handle dynamic and irregular graph applications.

Findings

Achieves up to 36x speedup over classic CGRAs.

Maintains similar energy efficiency to state-of-the-art graph processors.

Offers 2.2x better area efficiency with reduced power/area budget.

Abstract

Coarse-Grained Reconfigurable Arrays (CGRA) are promising edge accelerators due to the outstanding balance in flexibility, performance, and energy efficiency. Classic CGRAs statically map compute operations onto the processing elements (PE) and route the data dependencies among the operations through the Network-on-Chip. However, CGRAs are designed for fine-grained static instruction-level parallelism and struggle to accelerate applications with dynamic and irregular data-level parallelism, such as graph processing. To address this limitation, we present Flip, a novel accelerator that enhances traditional CGRA architectures to boost the performance of graph applications. Flip retains the classic CGRA execution model while introducing a special data-centric mode for efficient graph processing. Specifically, it exploits the natural data parallelism of graph algorithms by mapping graph vertices onto processing elements (PEs) rather than the operations, and supporting dynamic routing of temporary data according to the runtime evolution of the graph frontier. Experimental results demonstrate that Flip achieves up to 36$\times$ speedup with merely 19% more area compared to classic CGRAs. Compared to state-of-the-art large-scale graph processors, Flip has similar energy efficiency and 2.2$\times$ better area efficiency at a much-reduced power/area budget.