Fast and reconfigurable sort-in-memory system enabled by memristors
Lianfeng Yu, Yaoyu Tao, Teng Zhang, Zeyu Wang, Xile Wang, Zelun Pan,, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Yihang Zhu, Bonan Yan and, Yuchao Yang

TL;DR
This paper introduces a fast, reconfigurable sort-in-memory system using memristors, achieving significant speed, energy, and area improvements over traditional systems, and demonstrating practical applications like shortest path search and neural network inference.
Contribution
The paper presents a novel memristor-based sort-in-memory system with digit read and tree node skipping techniques, enabling efficient, reconfigurable sorting within memory arrays.
Findings
Up to 7.70x speedup over state-of-the-art systems
Energy efficiency improved by up to 183.5x
Area reduced by up to 7.43x
Abstract
Sorting is fundamental and ubiquitous in modern computing systems. Hardware sorting systems are built based on comparison operations with Von Neumann architecture, but their performance are limited by the bandwidth between memory and comparison units and the performance of complementary metal-oxide-semiconductor (CMOS) based circuitry. Sort-in-memory (SIM) based on emerging memristors is desired but not yet available due to comparison operations that are challenging to be implemented within memristive memory. Here we report fast and reconfigurable SIM system enabled by digit read (DR) on 1-transistor-1-resistor (1T1R) memristor arrays. We develop DR tree node skipping (TNS) that support variable data quantity and data types, and extend TNS with multi-bank, bit-slice and multi-level strategies to enable cross-array TNS (CA-TNS) for practical adoptions. Experimented on benchmark sorting…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · CCD and CMOS Imaging Sensors · Ferroelectric and Negative Capacitance Devices
