A Read Margin Enhancement Circuit with Dynamic Bias Optimization for MRAM

TL;DR

This paper presents a dynamic bias optimization circuit for MRAM that adaptively adjusts read voltage in real-time, significantly improving read margin, reducing error rates, and enhancing reliability across process and temperature variations.

Contribution

A novel dynamic bias optimization circuit is proposed to track optimal read voltages in MRAM, improving read margin and error rates under PVT variations.

Findings

Tracking accuracy remains above 90% under voltage variations.

Up to two orders of magnitude reduction in bit error rate.

Effective enhancement of MRAM performance and reliability.

Abstract

This brief introduces a read bias circuit to improve readout yield of magnetic random access memories (MRAMs). A dynamic bias optimization (DBO) circuit is proposed to enable the real-time tracking of the optimal read voltage across processvoltage-temperature (PVT) variations within an MRAM array. It optimizes read performance by adjusting the read bias voltage dynamically for maximum sensing margin. Simulation results on a 28-nm 1Mb MRAM macro show that the tracking accuracy of the proposed DBO circuit remains above 90% even when the optimal sensing voltage varies up to 50%. Such dynamic tracking strategy further results in up to two orders of magnitude reduction in the bit error rate with respect to different variations, highlighting its effectiveness in enhancing MRAM performance and reliability.