Rewriting History: Repurposing Domain-Specific CGRAs

TL;DR

FlexC is a novel compiler for CGRAs that uses dataflow rewriting and equality saturation to adapt unsupported operations, significantly increasing the number of accelerated kernels and achieving notable speedups.

Contribution

Introduces FlexC, the first flexible CGRA compiler that enables adaptation to unsupported operations through dataflow rewriting and equality saturation.

Findings

2.2× increase in supported loop kernels

3× speedup over Arm A5 CPU on unsupported kernels

Applied to over 2,000 loop kernels and multiple CGRAs

Abstract

Coarse-grained reconfigurable arrays (CGRAs) are domain-specific devices promising both the flexibility of FPGAs and the performance of ASICs. However, with restricted domains comes a danger: designing chips that cannot accelerate enough current and future software to justify the hardware cost. We introduce FlexC, the first flexible CGRA compiler, which allows CGRAs to be adapted to operations they do not natively support. FlexC uses dataflow rewriting, replacing unsupported regions of code with equivalent operations that are supported by the CGRA. We use equality saturation, a technique enabling efficient exploration of a large space of rewrite rules, to effectively search through the program-space for supported programs. We applied FlexC to over 2,000 loop kernels, compiling to four different research CGRAs and 300 generated CGRAs and demonstrate a 2.2$\times$ increase in the number of loop kernels accelerated leading to 3$\times$ speedup compared to an Arm A5 CPU on kernels that would otherwise be unsupported by the accelerator.