Comparative evaluation of bandwidth-bound applications on the Intel Xeon CPU MAX Series

TL;DR

This paper evaluates the performance of the Intel Xeon MAX CPU Series on bandwidth-sensitive HPC applications, comparing it to previous CPUs and analyzing the impact of architecture features and implementation choices.

Contribution

It provides a comprehensive performance analysis of the Intel Xeon MAX CPU Series for bandwidth-bound workloads, highlighting its advantages and bottlenecks compared to prior architectures.

Findings

Speedups of 2.0x to 4.3x over previous generation.

Performance bottlenecks shift from bandwidth to communication latency.

Performance varies with different parallel implementations and compiler configurations.

Abstract

In this paper we explore the performance of Intel Xeon MAX CPU Series, representing the most significant new variation upon the classical CPU architecture since the Intel Xeon Phi Processor. Given the availability of a large on-package high-bandwidth memory, the bandwidth-to-compute ratio has significantly shifted compared to other CPUs on the market. Since a large fraction of HPC workloads are sensitive to the available bandwidth, we explore how this architecture performs on a selection of HPC proxies and applications that are mostly sensitive to bandwidth, and how it compares to the previous 3rd generation Intel Xeon Scalable processors (codenamed Ice Lake) and an AMD EPYC 7003 Series Processor with 3D V-Cache Technology (codenamed Milan-X). We explore performance with different parallel implementations (MPI, MPI+OpenMP, MPI+SYCL), compiled with different compilers and flags, and executed with or without hyperthreading. We show how performance bottlenecks are shifted from bandwidth to communication latencies for some applications, and demonstrate speedups compared to the previous generation between 2.0x-4.3x.