A Low-Latency FFT-IFFT Cascade Architecture

TL;DR

This paper introduces a low-latency, buffer-free FFT-IFFT cascade architecture that reduces memory and latency by processing outputs ASAP, with extensions to multi-channel processing.

Contribution

It presents a novel folding set design for buffer-free FFT-IFFT cascades that minimizes latency and memory, extending to multi-channel interleaved processing.

Findings

Reduces memory by about N/2 units.

Lowers latency by about N/4 clock cycles.

Extends approach to multi-channel processing.

Abstract

This paper addresses the design of a partly-parallel cascaded FFT-IFFT architecture that does not require any intermediate buffer. Folding can be used to design partly-parallel architectures for FFT and IFFT. While many cascaded FFT-IFFT architectures can be designed using various folding sets for the FFT and the IFFT, for a specified folded FFT architecture, there exists a unique folding set to design the IFFT architecture that does not require an intermediate buffer. Such a folding set is designed by processing the output of the FFT as soon as possible (ASAP) in the folded IFFT. Elimination of the intermediate buffer reduces latency and saves area. The proposed approach is also extended to interleaved processing of multi-channel time-series. The proposed FFT-IFFT cascade architecture saves about N/2 memory elements and N/4 clock cycles of latency compared to a design with identical folding sets. For the 2-interleaved FFT-IFFT cascade, the memory and latency savings are, respectively, N/2 units and N/2 clock cycles, compared to a design with identical folding sets.