Characterization of the Intrinsic and Extrinsic Resistances of a Microwave Graphene FET Under Zero Transconductance Conditions

TL;DR

This paper analyzes the intrinsic and extrinsic resistances of a microwave graphene FET under zero transconductance conditions, providing a broadband model that aligns with experimental data and accounts for lossy gate capacitance.

Contribution

It introduces a comprehensive model for graphene FET resistances under specific conditions, including the effects of lossy gate capacitance, enhancing understanding of device behavior.

Findings

Resistances depend on gate and drain biases.

The model matches experimental data across a broad frequency range.

Lossy gate capacitance significantly affects device resistances.

Abstract

Graphene field-effect transistors exhibit negligible transconductance under two scenarios: for any gate-to-source voltage when the drain-to-source voltage is set to zero, and for an arbitrary drain-to-source voltage provided that the gate-to-source voltage equals the Dirac voltage. Hence, extracting the channel and the parasitic series resistances from S-parameters under these conditions enables analyzing their dependence on the gate and drain biases. This is fundamental to assess the portion of the output resistance that is controlled by the gate. Besides, the drain bias dependence of the drain and source resistances is also evidenced. Within the proposal, resistive components accounting for the lossy nature of the gate capacitance are incorporated into the model, which exhibits a broadband correlation with experimental data. This avoids the series resistances to be considered as frequency dependent in the model.