Optimized Implementation of Neuromorphic HATS Algorithm on FPGA

TL;DR

This paper introduces the first optimized FPGA hardware implementation of the neuromorphic HATS algorithm for event-based object classification, achieving low latency and high throughput with significant power efficiency.

Contribution

It presents a novel FPGA implementation of the HATS algorithm, optimizing for speed and power efficiency, and analyzes the tradeoffs involved.

Findings

Latency of 3.3 ms on N-CARS dataset

Processing capability of 2.94 million events per second

Approximately 32 times more power efficient than software

Abstract

In this paper, we present first-ever optimized hardware implementation of a state-of-the-art neuromorphic approach Histogram of Averaged Time Surfaces (HATS) algorithm to event-based object classification in FPGA for asynchronous time-based image sensors (ATIS). Our Implementation achieves latency of 3.3 ms for the N-CARS dataset samples and is capable of processing 2.94 Mevts/s. Speed-up is achieved by using parallelism in the design and multiple Processing Elements can be added. As development platform, Zynq-7000 SoC from Xilinx is used. The tradeoff between Average Absolute Error and Resource Utilization for fixed precision implementation is analyzed and presented. The proposed FPGA implementation is $\sim$ 32 x power efficient compared to software implementation.