Solving Partial Differential Equations with Monte Carlo / Random Walk on an Analog-Digital Hybrid Computer
Dirk Killat, Sven K\"oppel, Bernd Ulmann, Lucas Wetzel

TL;DR
This paper explores a hybrid analog-digital computing approach using random walks to solve specific partial differential equations, aiming to reduce power consumption and improve efficiency on future analog hardware.
Contribution
It introduces a novel random walk method tailored for hybrid analog-digital systems to efficiently solve PDEs, with experimental validation and power-saving estimates.
Findings
Demonstrated the method on an Analog Paradigm Model-1
Estimated potential speedups with future analog computers on chip
Showed reduced power consumption compared to traditional digital methods
Abstract
Current digital computers are about to hit basic physical boundaries with respect to integration density, clock frequencies, and particularly energy consumption. This requires the application of new computing paradigms, such as quantum and analog computing in the near future. Although neither quantum nor analog computer are general purpose computers they will play an important role as co-processors to offload certain classes of compute intensive tasks from classic digital computers, thereby not only reducing run time but also and foremost power consumption. In this work, we describe a random walk approach to the solution of certain types of partial differential equations which is well suited for combinations of digital and analog computers (hybrid computers). The experiments were performed on an Analog Paradigm Model-1 analog computer attached to a digital computer by means of a…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Parallel Computing and Optimization Techniques · Low-power high-performance VLSI design
