Multiplierless Design of High-Speed Very Large Constant Multiplications

TL;DR

This paper presents LEIGER, an automated tool for designing high-speed, low-complexity large constant multipliers in cryptography, optimizing hardware architecture to improve area, delay, and energy efficiency.

Contribution

LEIGER introduces a novel automated approach for multiplierless large constant multiplications, utilizing shift-adds, hybrid architectures, and compressor trees for ASIC design.

Findings

LEIGER achieves better area-delay product than recent algorithms.

The tool effectively explores trade-offs between area, delay, and energy.

Case study on Montgomery multiplication demonstrates high-speed, efficient designs.

Abstract

In cryptographic algorithms, the constants to be multiplied by a variable can be very large due to security requirements. Thus, the hardware complexity of such algorithms heavily depends on the design architecture handling large constants. In this paper, we introduce an electronic design automation tool, called LEIGER, which can automatically generate the realizations of very large constant multiplications for low-complexity and high-speed applications, targeting the ASIC design platform. LEIGER can utilize the shift-adds architecture and use 3-input operations, i.e., carry-save adders (CSAs), where the number of CSAs is reduced using a prominent optimization algorithm. It can also generate constant multiplications under a hybrid design architecture, where 2-and 3-input operations are used at different stages. Moreover, it can describe constant multiplications under a design architecture using compressor trees. As a case study, high-speed Montgomery multiplication, which is a fundamental operation in cryptographic algorithms, is designed with its constant multiplication block realized under the proposed architectures. Experimental results indicate that LEIGER enables a designer to explore the trade-off between area and delay of the very large constant and Montgomery multiplications and leads to designs with area-delay product, latency, and energy consumption values significantly better than those obtained by a recently proposed algorithm.