PyHGL: A Python-based Hardware Generation Language Framework

TL;DR

PyHGL is a Python-based hardware generation framework that simplifies hardware design, enhances productivity, and efficiently simulates asynchronous circuits with integrated verification features.

Contribution

PyHGL introduces a unified Python-based environment for hardware generation, simulation, and verification, with novel features supporting asynchronous circuits and reducing code complexity.

Findings

PyHGL code is up to 6.1x denser than traditional RTL.

The integrated simulator achieves 2.9x speedup.

PyHGL generates high-quality, synthesizable RTL code.

Abstract

Hardware generation languages (HGLs) increase hardware design productivity by creating parameterized modules and test benches. Unfortunately, existing tools are not widely adopted due to several demerits, including limited support for asynchronous circuits and unknown states, lack of concise and efficient language features, and low integration of simulation and verification functions. This paper introduces PyHGL, an open-source Python framework that aims to provide a simple and unified environment for hardware generation, simulation, and verification. PyHGL language is a syntactical superset of Python, which greatly reduces the lines of code (LOC) and improves productivity by providing unique features such as dynamic typing, vectorized operations, and automatic port deduction. In addition, PyHGL integrates an event-driven simulator that simulates the asynchronous behaviors of digital circuits using three-state logic. We also propose an algorithm that eliminates the calculation and transmission overhead of unknown state propagation for binary stimuli. The results suggest that PyHGL code is up to 6.1x denser than traditional RTL and generates high-quality synthesizable RTL code. Moreover, the optimized simulator achieves 2.9x speed up and matches the performance of a commonly used open-source logic simulator.