High-Speed (7,2) Compressor Using A Fast Carry-Generation Logic based on Sorting Network

TL;DR

This paper introduces a high-speed (7,2) compressor with a novel carry-generation logic based on sorting networks, significantly reducing logical stages and improving performance for digital arithmetic and cryptography hardware.

Contribution

A new (7,2) compressor design using sorting network-based carry logic that reduces logical stages from 3 to 2, enhancing speed and efficiency.

Findings

Achieves carry generation within 2 logical stages

Uses only 11 logical stages in total

Demonstrates higher performance in binary array testing

Abstract

Fast binary compressors are the main components of many basic digital calculation units. In this paper, a high-speed (7,2) compressor with a fast carry-generation logic is proposed. The carry-generation logic is based on the sorting network, and it can generate a carry bit within 2 logical stages other than 3 stages as in previous school book full adders. Collaborating with the adjusted full adder logic, the proposed (7,2) compressor achieves using only 11 basic logical stages. Testing this new design in a binary arry with 7 rows and 8 columns, and the result shows that this design have higher proformance than previous designs. This method is suitable for high proformance cases in multiplication design or other cryptography hardware blocks.