A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation

TL;DR

This paper introduces a novel 9T SRAM cell design that enables array-level XOR parallelism and secure data toggling, significantly improving energy efficiency and security for edge computing applications.

Contribution

A new 9T SRAM architecture that allows parallel XOR operations across multiple rows and incorporates secure data toggling to prevent imprinting and remanence attacks.

Findings

Enables array-wide XOR in a single cycle

Supports secure data toggling within SRAM cells

Improves energy efficiency and security in edge computing

Abstract

Security and energy-efficiency are critical for computing applications in general and for edge applications in particular. Digital in-Memory Computing (IMC) in SRAM cells have widely been studied to accelerate inference tasks to maximize both throughput and energy efficiency for intelligent computing at the edge. XOR operations have been of particular interest due to their wide applicability in numerous applications that include binary neural networks and encryption. However, existing IMC circuits for XOR acceleration are limited to two rows in a memory array and extending the XOR parallelism to multiple rows in an SRAM array has remained elusive. Further, SRAM is prone to both data imprinting and data remanence security issues, which poses limitations on security . Based on commerical Globalfoundries 22nm mode, we are proposing a novel 9T SRAM cell such that multiple rows of data (entire array) can be XORed in a massively parallel single cycle fashion. The new cell also supports data-toggling within the SRAM cell efficiently to circumvent imprinting attacks and erase the SRAM value in case of remanence attack.