Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators

TL;DR

This paper presents an ILP-based automatic scheduler for high-level synthesis that enables multi-dimensional pipelining, significantly improving performance and resource efficiency in dataflow accelerators for edge computing workloads.

Contribution

It introduces a unified ILP formulation for multi-dimensional pipelining, handling complex memory access patterns and integrating with MLIR-based HLS frameworks.

Findings

Achieves an average of 2.42X performance improvement over Vitis HLS with loop pipelining.

Achieves an average of 1.30X performance improvement over Vitis HLS with dataflow optimizations.

Reduces overall execution latency through aggressive multi-dimensional pipelining.

Abstract

In recent years, there has been a surging demand for edge computing of image processing and machine learning workloads. This has reignited interest in the development of custom hardware accelerators that can deliver enhanced performance and improved energy efficiency. These workloads frequently demonstrate affine memory accesses and constant loop bounds. In this paper, we introduce an ILP-based automatic scheduler for high-level synthesis, with a specific emphasis on aggressive pipelining to enhance parallelism. In this study, we propose a unified Integer Linear Programming (ILP) formulation that can identify pipelining opportunities along multiple loop and scalar dimensions. Our multi-dimensional pipelining technique encompasses both inner loop pipelining and dataflow optimizations of Vitis HLS, while also being capable of handling more general memory access patterns compared to the dataflow optimization in Vitis HLS. Furthermore, our approach enables the generation of statically scheduled circuits, leading to improved resource efficiency. We have integrated our scheduler into a high-level synthesis compiler framework (HIR) based on MLIR and conducted performance evaluations. Our findings reveal that our scheduler, in comparison to Vitis HLS, can achieve more aggressive pipelining across multiple producer-consumer loop nests, resulting in reduced overall execution latency. The producer-consumer pipelined execution facilitated by our scheduler yields an average performance improvement of 2.42X across a set of representative benchmarks when compared to only loop pipelining. Furthermore, we achieved an average performance improvement of 1.30X over Vitis HLS with dataflow optimizations.