Low disorder and high valley splitting in silicon

TL;DR

This paper demonstrates that a co-design approach to silicon quantum well structures can simultaneously achieve low disorder and high valley splitting, improving the performance potential of silicon-based quantum dot qubits.

Contribution

It introduces a co-design methodology for silicon quantum wells that enhances both disorder and valley splitting, surpassing traditional reductionist approaches.

Findings

High mobility of 3.14×10^5 cm^2/Vs in quantum wells

Low charge noise of 0.9 μeV/Hz^1/2 in quantum dots

Mean valley splitting energy of 0.24 meV in qubit devices

Abstract

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically-purified, strained quantum wells with high mobility of 3.14(8)$\times$10$^5$ cm$^2$/Vs and low percolation density of 6.9(1)$\times$10$^{10}$ cm$^{-2}$. These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) $\mu$eV/Hz$^{1/2}$ and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.