HW/SW Codesign for Robust and Efficient Binarized SNNs by Capacitor Minimization
Mikail Yayla, Simon Thomann, Ming-Liang Wei, Chia-Lin Yang, Jian-Jia, Chen, Hussam Amrouch

TL;DR
This paper introduces CapMin, a hardware/software co-design approach that significantly reduces capacitor size in analog IF-SNNs, improving energy efficiency and robustness against variations.
Contribution
CapMin is a novel method that minimizes capacitor size by reducing spike times based on frequency analysis, enhancing analog SNN efficiency.
Findings
Over 14x reduction in capacitor size compared to state-of-the-art
CapMin-V increases variation tolerance with minimal capacitor size increase
Improves energy efficiency and robustness of analog IF-SNNs
Abstract
Using accelerators based on analog computing is an efficient way to process the immensely large workloads in Neural Networks (NNs). One example of an analog computing scheme for NNs is Integrate-and-Fire (IF) Spiking Neural Networks (SNNs). However, to achieve high inference accuracy in IF-SNNs, the analog hardware needs to represent current-based multiply-accumulate (MAC) levels as spike times, for which a large membrane capacitor needs to be charged for a certain amount of time. A large capacitor results in high energy use, considerable area cost, and long latency, constituting one of the major bottlenecks in analog IF-SNN implementations. In this work, we propose a HW/SW Codesign method, called CapMin, for capacitor size minimization in analog computing IF-SNNs. CapMin minimizes the capacitor size by reducing the number of spike times needed for accurate operation of the HW, based on…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neural Networks and Reservoir Computing
