On-Chip Hardware-Aware Quantization for Mixed Precision Neural Networks

TL;DR

This paper introduces an on-chip hardware-aware quantization framework for mixed-precision neural networks, enabling accurate and efficient deployment on edge devices by directly measuring hardware efficiency and estimating accuracy impacts without relying on high-performance simulations.

Contribution

It proposes a novel on-chip quantization pipeline and mask-guided accuracy estimation to optimize mixed-precision models directly on hardware, reducing reliance on simulations and high-power computing.

Findings

Achieves 70% and 73% accuracy on ResNet-18 and MobileNetV3.

Reduces latency by 15-30% compared to INT8 quantization.

Operates effectively on various architectures and compression ratios.

Abstract

Low-bit quantization emerges as one of the most promising compression approaches for deploying deep neural networks on edge devices. Mixed-precision quantization leverages a mixture of bit-widths to unleash the accuracy and efficiency potential of quantized models. However, existing mixed-precision quantization methods rely on simulations in high-performance devices to achieve accuracy and efficiency trade-offs in immense search spaces. This leads to a non-negligible gap between the estimated efficiency metrics and the actual hardware that makes quantized models far away from the optimal accuracy and efficiency, and also causes the quantization process to rely on additional high-performance devices. In this paper, we propose an On-Chip Hardware-Aware Quantization (OHQ) framework, performing hardware-aware mixed-precision quantization on deployed edge devices to achieve accurate and efficient computing. Specifically, for efficiency metrics, we built an On-Chip Quantization Aware pipeline, which allows the quantization process to perceive the actual hardware efficiency of the quantization operator and avoid optimization errors caused by inaccurate simulation. For accuracy metrics, we propose Mask-Guided Quantization Estimation technology to effectively estimate the accuracy impact of operators in the on-chip scenario, getting rid of the dependence of the quantization process on high computing power. By synthesizing insights from quantized models and hardware through linear optimization, we can obtain optimized bit-width configurations to achieve outstanding performance on accuracy and efficiency. We evaluate inference accuracy and acceleration with quantization for various architectures and compression ratios on hardware. OHQ achieves 70% and 73% accuracy for ResNet-18 and MobileNetV3, respectively, and can reduce latency by 15~30% compared to INT8 on real deployment.