ADC/DAC-Free Analog Acceleration of Deep Neural Networks with Frequency Transformation

TL;DR

This paper introduces an energy-efficient analog acceleration method for frequency-domain neural networks that eliminates the need for ADC/DAC components, leveraging frequency transformations and parallel micro-architecture for high performance.

Contribution

It proposes a novel ADC/DAC-free analog tensor transformation approach with adaptive micro-architecture, enabling efficient, parameter-free, and highly parallel frequency-domain neural network processing.

Findings

Achieves 1602 TOPS/W energy efficiency without early termination.

Reaches 5311 TOPS/W energy efficiency with early termination.

Supports signed-bit processing for increased sparsity.

Abstract

The edge processing of deep neural networks (DNNs) is becoming increasingly important due to its ability to extract valuable information directly at the data source to minimize latency and energy consumption. Frequency-domain model compression, such as with the Walsh-Hadamard transform (WHT), has been identified as an efficient alternative. However, the benefits of frequency-domain processing are often offset by the increased multiply-accumulate (MAC) operations required. This paper proposes a novel approach to an energy-efficient acceleration of frequency-domain neural networks by utilizing analog-domain frequency-based tensor transformations. Our approach offers unique opportunities to enhance computational efficiency, resulting in several high-level advantages, including array micro-architecture with parallelism, ADC/DAC-free analog computations, and increased output sparsity. Our approach achieves more compact cells by eliminating the need for trainable parameters in the transformation matrix. Moreover, our novel array micro-architecture enables adaptive stitching of cells column-wise and row-wise, thereby facilitating perfect parallelism in computations. Additionally, our scheme enables ADC/DAC-free computations by training against highly quantized matrix-vector products, leveraging the parameter-free nature of matrix multiplications. Another crucial aspect of our design is its ability to handle signed-bit processing for frequency-based transformations. This leads to increased output sparsity and reduced digitization workload. On a 16$\times$16 crossbars, for 8-bit input processing, the proposed approach achieves the energy efficiency of 1602 tera operations per second per Watt (TOPS/W) without early termination strategy and 5311 TOPS/W with early termination strategy at VDD = 0.8 V.