A balanced Memristor-CMOS ternary logic family and its application

TL;DR

This paper introduces a balanced memristor-CMOS ternary logic family, designing fundamental gates and complex circuits, and compares two implementation schemes to guide future three-valued logic circuit development.

Contribution

It presents systematic design and simulation of balanced ternary logic gates and circuits using memristors and CMOS, along with comparative analysis of two design schemes.

Findings

Two design schemes are compared and analyzed.

Balanced ternary logic circuits are successfully implemented and verified.

The study provides insights for future three-valued logic circuit research.

Abstract

The design of balanced ternary digital logic circuits based on memristors and conventional CMOS devices is proposed. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are systematically designed and verified by simulation, and then logic circuits such as ternary encoders, decoders and multiplexers are designed on this basis. Two different schemes are then used to realize the design of functional combinational logic circuits such as a balanced ternary half adder, multiplier, and numerical comparator. Finally, we report a series of comparisons and analyses of the two design schemes, which provide a reference for subsequent research and development of three-valued logic circuits.