SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices

TL;DR

SATAY introduces a streaming FPGA architecture and automated toolflow that accelerates YOLO object detection models, enabling real-time, low-latency inference suitable for edge devices with competitive performance and energy efficiency.

Contribution

The paper presents a novel streaming architecture and automated FPGA toolflow for YOLO models, supporting deep pipelining and hardware innovations to enhance performance and energy efficiency.

Findings

Achieves real-time object detection on FPGA with low latency

Outperforms existing FPGA accelerators in performance and energy efficiency

Supports a range of FPGA devices with automated design generation

Abstract

AI has led to significant advancements in computer vision and image processing tasks, enabling a wide range of applications in real-life scenarios, from autonomous vehicles to medical imaging. Many of those applications require efficient object detection algorithms and complementary real-time, low latency hardware to perform inference of these algorithms. The YOLO family of models is considered the most efficient for object detection, having only a single model pass. Despite this, the complexity and size of YOLO models can be too computationally demanding for current edge-based platforms. To address this, we present SATAY: a Streaming Architecture Toolflow for Accelerating YOLO. This work tackles the challenges of deploying stateof-the-art object detection models onto FPGA devices for ultralow latency applications, enabling real-time, edge-based object detection. We employ a streaming architecture design for our YOLO accelerators, implementing the complete model on-chip in a deeply pipelined fashion. These accelerators are generated using an automated toolflow, and can target a range of suitable FPGA devices. We introduce novel hardware components to support the operations of YOLO models in a dataflow manner, and off-chip memory buffering to address the limited on-chip memory resources. Our toolflow is able to generate accelerator designs which demonstrate competitive performance and energy characteristics to GPU devices, and which outperform current state-of-the-art FPGA accelerators.