Accelerating LSTM-based High-Rate Dynamic System Models

TL;DR

This paper demonstrates how an FPGA-optimized LSTM model can achieve sub-microsecond latency for real-time structural health monitoring, significantly improving computational efficiency over traditional Euler-Bernoulli models.

Contribution

It introduces an FPGA deployment of an LSTM surrogate model for high-rate dynamic system simulation, achieving unprecedented low latency suitable for active structural control.

Findings

Achieved 1.42 microsecond latency on FPGA

Reached 7.87 Gops/s throughput

Validated LSTM as an efficient surrogate for Euler-Bernoulli models

Abstract

In this paper, we evaluate the use of a trained Long Short-Term Memory (LSTM) network as a surrogate for a Euler-Bernoulli beam model, and then we describe and characterize an FPGA-based deployment of the model for use in real-time structural health monitoring applications. The focus of our efforts is the DROPBEAR (Dynamic Reproduction of Projectiles in Ballistic Environments for Advanced Research) dataset, which was generated as a benchmark for the study of real-time structural modeling applications. The purpose of DROPBEAR is to evaluate models that take vibration data as input and give the initial conditions of the cantilever beam on which the measurements were taken as output. DROPBEAR is meant to serve an exemplar for emerging high-rate "active structures" that can be actively controlled with feedback latencies of less than one microsecond. Although the Euler-Bernoulli beam model is a well-known solution to this modeling problem, its computational cost is prohibitive for the time scales of interest. It has been previously shown that a properly structured LSTM network can achieve comparable accuracy with less workload, but achieving sub-microsecond model latency remains a challenge. Our approach is to deploy the LSTM optimized specifically for latency on FPGA. We designed the model using both high-level synthesis (HLS) and hardware description language (HDL). The lowest latency of 1.42 $\mu$S and the highest throughput of 7.87 Gops/s were achieved on Alveo U55C platform for HDL design.