Bayesian Integration of Information Using Top-Down Modulated WTA Networks

TL;DR

This paper investigates how top-down processes can enhance WTA neural networks' ability to integrate information and perform Bayesian inference, aligning with neuroscientific evidence and neuromorphic principles.

Contribution

It demonstrates that WTA circuits can incorporate top-down information to improve inference and learning, extending previous bottom-up focused models.

Findings

WTA circuits can integrate probabilistic information from other WTA networks.

Top-down processes enhance WTA inference and learning performance.

The approach is suitable for low-latency, energy-efficient neuromorphic hardware.

Abstract

Winner Take All (WTA) circuits a type of Spiking Neural Networks (SNN) have been suggested as facilitating the brain's ability to process information in a Bayesian manner. Research has shown that WTA circuits are capable of approximating hierarchical Bayesian models via Expectation Maximization (EM). So far, research in this direction has focused on bottom up processes. This is contrary to neuroscientific evidence that shows that, besides bottom up processes, top down processes too play a key role in information processing by the human brain. Several functions ascribed to top down processes include direction of attention, adjusting for expectations, facilitation of encoding and recall of learned information, and imagery. This paper explores whether WTA circuits are suitable for further integrating information represented in separate WTA networks. Furthermore, it explores whether, and under what circumstances, top down processes can improve WTA network performance with respect to inference and learning. The results show that WTA circuits are capable of integrating the probabilistic information represented by other WTA networks, and that top down processes can improve a WTA network's inference and learning performance. Notably, it is able to do this according to key neuromorphic principles, making it ideal for low-latency and energy efficient implementation on neuromorphic hardware.