PALS: Distributed Gradient Clocking on Chip

TL;DR

This paper introduces PALS, a distributed gradient clock synchronization method for on-chip networks that achieves near-oscillator frequency bounds with minimal phase offset, improving local clock coordination.

Contribution

It presents a novel distributed gradient clock synchronization algorithm that balances between centralized and asynchronous solutions for on-chip modules.

Findings

Achieves phase offsets smaller than one clock cycle between neighboring modules.

Provides frequency bounds close to free-running oscillators.

Mathematically bounds phase offset at 20ps in a 32x32 network at 2GHz.

Abstract

Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: (i) by deriving it from a single, central clock source, (ii) by local, free-running oscillators, or (iii) by handshaking between neighboring modules. Conceptually, each of these solutions is the result of a perceived dichotomy in which (sub)systems are either clocked or asynchronous. We present a solution and its implementation that lies between these extremes. Based on a distributed gradient clock synchronization algorithm, we show a novel design providing modules with local clocks, the frequency bounds of which are almost as good as those of free-running oscillators, yet neighboring modules are guaranteed to have a phase offset substantially smaller than one clock cycle. Concretely, parameters obtained from a 15nm ASIC simulation running at 2GHz yield mathematical worst-case bounds of 20ps on the phase offset for a $32 \times 32$ node grid network.