Area Efficient Modular Reduction in Hardware for Arbitrary Static Moduli
Robin M\"uller, Willi Meier, Christoph F. Wildfeuer

TL;DR
This paper introduces a hardware-efficient modular reduction method for static moduli that reduces area consumption significantly, avoids multiplications, and enhances security through constant-time execution, benefiting post-quantum cryptography implementations.
Contribution
A novel hardware modular reduction technique for arbitrary static moduli that eliminates multiplications and reduces area, suitable for parallelization and secure cryptographic applications.
Findings
Reduces hardware area by up to 90% compared to Barrett methods.
Operates in constant time to prevent timing attacks.
Scales linearly with operation width and is suitable for parallel and pipelined hardware.
Abstract
Modular reduction is a crucial operation in many post-quantum cryptographic schemes, including the Kyber key exchange method or Dilithium signature scheme. However, it can be computationally expensive and pose a performance bottleneck in hardware implementations. To address this issue, we propose a novel approach for computing modular reduction efficiently in hardware for arbitrary static moduli. Unlike other commonly used methods such as Barrett or Montgomery reduction, the method does not require any multiplications. It is not dependent on properties of any particular choice of modulus for good performance and low area consumption. Its major strength lies in its low area consumption, which was reduced by 60% for optimized and up to 90% for generic Barrett implementations for Kyber and Dilithium. Additionally, it is well suited for parallelization and pipelining and scales linearly in…
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Taxonomy
TopicsCryptography and Data Security · Coding theory and cryptography · Cryptographic Implementations and Security
