A Novel Reconfigurable Vector-Processed Interleaving Algorithm for a DVB-RCS2 Turbo Encoder

TL;DR

This paper introduces a reconfigurable parallel interleaving algorithm for DVB-RCS2 Turbo Encoders, significantly reducing processing delays and improving speed compared to traditional serial methods.

Contribution

It presents a novel reconfigurable vector-processed interleaving algorithm that enhances Turbo Encoder performance by leveraging DSP attributes for parallel processing.

Findings

Achieved up to 3.4x speed-up in total cycles

Realized 4.8x faster write operations

Attained 7.3x faster read operations

Abstract

Turbo-Codes (TC) are a family of convolutional codes enabling Forward-Error-Correction (FEC) while approaching the theoretical limit of channel capacity predicted by Shannons theorem. One of the bottlenecks of a Turbo Encoder (TE) lies in the non-uniform interleaving stage. Interleaving algorithms require stalling the input vector bits before the bit rearrangement causing a delay in the overall process. This paper presents performance enhancement via a parallel algorithm for the interleaving stage of a Turbo Encoder application compliant with the DVB-RCS2 standard. The algorithm efficiently implements the interleaving operation while utilizing attributes of a given DSP. We will discuss and compare a serial model for the TE, with the presented parallel processed algorithm. Results showed a speed-up factor of up to 3.4 Total-Cycles, 4.8 Write and 7.3 Read.