Implementing Performance Portability of High Performance Computing Programs in the New Golden Age of Chip Architecture
Weifeng Liu, Linping Wu, Xiaowen Xu, Yuren Wang

TL;DR
This paper reviews current techniques for achieving performance portability in high-performance computing across diverse hardware architectures, emphasizing programming models, automatic parallelization, and library use.
Contribution
It provides a comprehensive summary of existing performance portability technologies and discusses how to select suitable solutions based on application scenarios.
Findings
Different architectures require tailored performance portability strategies.
Using scientific computing libraries enhances performance portability.
Trade-offs exist between programming efficiency and optimization.
Abstract
As an important goal of high-performance computing, the concept of performance portability has been around for many years. As the failure of Moore's Law, it is no longer feasible to improve computer performance by simply increasing the number of existing hardware. The innovation of high performance computer is imperative, which makes high-performance computers with multiple architectures coexist in the production environment. For example, current high-performance computing nodes often use co-accelerators such like general-purpose GPUs and Intel Xeon Phis to accelerate general-purpose processors. With the flourishing of deep learning, dedicated neural network acceleration chips are also arising. The emergence of co-accelerators with different architectures and their wide application in high-performance computers have challenged the performance portability of programs between…
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Taxonomy
TopicsDistributed and Parallel Computing Systems · Cloud Computing and Resource Management · Parallel Computing and Optimization Techniques
