Valley-Free Silicon Fins Caused by Shear Strain

TL;DR

This paper presents CMOS-compatible silicon fin transistors with large shear strain that significantly increase valley energy gaps, removing troublesome valley states and enabling scalable silicon quantum computing architectures.

Contribution

The authors introduce a novel device design using shear strain in silicon-germanium nanostructures to eliminate valley degeneracy, improving scalability of silicon quantum computers.

Findings

Valley energy gaps are increased by over an order of magnitude.

Troublesome valley states are completely removed in the proposed design.

Valley energies can be tuned in situ with electric fields.

Abstract

Electron spins confined in silicon quantum dots are promising candidates for large-scale quantum computers. However, the degeneracy of the conduction band of bulk silicon introduces additional levels dangerously close to the window of computational energies, where the quantum information can leak. The energy of the valley states -- typically 0.1 meV -- depends on hardly controllable atomistic disorder and still constitutes a fundamental limit to the scalability of these architectures. In this work, we introduce designs of complementary metal-oxide-semiconductor (CMOS)-compatible silicon fin field-effect transistors that enhance the energy gap to noncomputational states by more than one order of magnitude. Our devices comprise realistic silicon-germanium nanostructures with a large shear strain, where troublesome valley degrees of freedom are completely removed. The energy of noncomputational states is therefore not affected by unavoidable atomistic disorder and can further be tuned in situ by applied electric fields. Our design ideas are directly applicable to a variety of setups and will offer a blueprint toward silicon-based large-scale quantum processors.