An Intermediate Representation for Composable Typed Streaming Dataflow Designs

TL;DR

This paper introduces an open-source intermediate representation for Tydi, a data-centric streaming dataflow specification, enabling better component reuse, interface definition, and system collaboration in hardware design.

Contribution

It presents a new IR for Tydi types and Streamlets, supporting reuse, high-level interface specification, and integration with hardware design tools, along with a verification syntax and a VHDL backend.

Findings

IR supports component reuse and interface contracts.

The system includes a grammar, parser, and query tools.

A VHDL backend demonstrates practical application.

Abstract

Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. These data types are extensively used in a many application domains, such as big data and SQL applications. This way, Tydi provides a higher-level method for defining interfaces between components as opposed to existing bit and byte-based interface specifications. In this paper, we introduce an open-source intermediate representation (IR) which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi's streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system. The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior. To demonstrate this IR, we have created a grammar, parser, and query system, and paired these with a backend targeting VHDL.