Design and execution of quantum circuits using tens of superconducting qubits and thousands of gates for dense Ising optimization problems

TL;DR

This paper presents a hardware-efficient variational quantum circuit design for dense Ising problems, demonstrating improved performance on a 50-qubit superconducting processor despite noise, with up to 5000 gates.

Contribution

It introduces a novel ansatz that parametrizes interactions and gate orderings, showing experimental performance gains on a real quantum device.

Findings

Performance improves with circuit depth and parameters.

Achieves better results than random guessing for circuits with thousands of gates.

Gate orderings as variational parameters significantly boost performance.

Abstract

We develop a hardware-efficient ansatz for variational optimization, derived from existing ansatze in the literature, that parametrizes subsets of all interactions in the Cost Hamiltonian in each layer. We treat gate orderings as a variational parameter and observe that doing so can provide significant performance boosts in experiments. We carried out experimental runs of a compilation-optimized implementation of fully-connected Sherrington-Kirkpatrick Hamiltonians on a 50-qubit linear-chain subsystem of Rigetti Aspen-M-3 transmon processor. Our results indicate that, for the best circuit designs tested, the average performance at optimized angles and gate orderings increases with circuit depth (using more parameters), despite the presence of a high level of noise. We report performance significantly better than using a random guess oracle for circuits involving up to approx 5000 two-qubit and approx 5000 one-qubit native gates. We additionally discuss various takeaways of our results toward more effective utilization of current and future quantum processors for optimization.