GSA to HDL: Towards principled generation of dynamically scheduled circuits

TL;DR

This paper introduces h-GSA, an extension of GSA IR, enabling more efficient hardware mapping for dynamically scheduled circuits in high-level synthesis, leading to potential performance improvements over existing tools.

Contribution

We propose h-GSA, a new IR abstraction that improves the translation of high-level programs into dynamically scheduled hardware circuits, enhancing performance.

Findings

h-GSA enables more efficient hardware mapping.

The approach shows potential performance gains over Dynamatic.

The method formalizes the translation process for dynamic scheduling.

Abstract

High-level synthesis (HLS) refers to the automatic translation of a software program written in a high-level language into a hardware design. Modern HLS tools have moved away from the traditional approach of static (compile time) scheduling of operations to generating dynamic circuits that schedule operations at run time. Such circuits trade-off area utilisation for increased dynamism and throughput. However, existing lowering flows in dynamically scheduled HLS tools rely on conservative assumptions on their input program due to both the intermediate representations (IR) utilised as well as the lack of formal specifications on the translation into hardware. These assumptions cause suboptimal hardware performance. In this work, we lift these assumptions by proposing a new and efficient abstraction for hardware mapping; namely h-GSA, an extension of the Gated Single Static Assignment (GSA) IR. Using this abstraction, we propose a lowering flow that transforms GSA into h-GSA and maps h-GSA into dynamically scheduled hardware circuits. We compare the schedules generated by our approach to those by the state-of-the-art dynamic-scheduling HLS tool, Dynamatic, and illustrate the potential performance improvement from hardware mapping using the proposed abstraction.