Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs

TL;DR

This paper demonstrates the first on-chip implementation of a p-bit core using stochastic Magnetic Tunnel Junctions integrated with 2D-MoS2 FETs, enabling voltage-controlled stochasticity for probabilistic computing.

Contribution

It introduces a novel integrated p-bit design combining stochastic MTJs with 2D-MoS2 FETs and provides a detailed analysis of component interactions influencing p-bit output.

Findings

First on-chip realization of a p-bit with voltage-controllable stochasticity.

Analysis of the impact of transistor and MTJ characteristics on p-bit performance.

Design rules for future scalable on-chip p-bit networks.

Abstract

Probabilistic computing is a novel computing scheme that offers a more efficient approach than conventional CMOS-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic-bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic Magnetic Tunnel Junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, through integrating stochastic MTJs with 2D-MoS$_{2}$ FETs, the first on-chip realization of a key p-bit building block displaying voltage-controllable stochasticity is demonstrated. In addition, supported by circuit simulations, this work provides a careful analysis of the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. This understanding of the interplay between the characteristics of the transistors and the MTJ is vital for the construction of a fully functioning p-bit, making the design rules presented in this article key for future experimental implementations of scaled on-chip p-bit networks.