Constrained Bayesian Optimization Using a Lagrange Multiplier Applied to Power Transistor Design

TL;DR

This paper introduces a constrained Bayesian Optimization method using a Lagrange multiplier to efficiently optimize LDMOS transistor designs with specific breakdown voltage constraints, eliminating the need for separate constraint surrogates.

Contribution

The paper presents a novel constrained BO algorithm that incorporates the Lagrange multiplier directly into the objective, enabling efficient optimization of device performance under constraints without additional models.

Findings

Successfully optimized LDMOS devices with target BV and FOM constraints.

Explored physical limits of FOM in 30-50 V range.

Demonstrated the algorithm's effectiveness in device design.

Abstract

We propose a novel constrained Bayesian Optimization (BO) algorithm optimizing the design process of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors while realizing a target Breakdown Voltage (BV). We convert the constrained BO problem into a conventional BO problem using a Lagrange multiplier. Instead of directly optimizing the traditional Figure-of-Merit (FOM), we set the Lagrangian as the objective function of BO. This adaptive objective function with a changeable Lagrange multiplier can address constrained BO problems which have constraints that require costly evaluations, without the need for additional surrogate models to approximate constraints. Our algorithm enables a device designer to set the target BV in the design space, and obtain a device that satisfies the optimized FOM and the target BV constraint automatically. Utilizing this algorithm, we have also explored the physical limits of the FOM for our devices in 30 - 50 V range within the defined design space.