The interface states in gate-all-around transistors (GAAFETs)

TL;DR

This paper introduces a multiscale simulation framework for GAAFETs that combines atomistic models and ab initio quantum calculations to analyze interface states and their impact on device performance.

Contribution

It presents a novel multiscale simulation framework bridging atomic-level calculations with commercial TCAD for GAAFETs.

Findings

Identified two new origins of interface states.

Showed how interface states can be tuned by device geometry.

Explained the preference for nanosheet channels in industry.

Abstract

The atomic-level structural detail and the quantum effects are becoming crucial to device performance as the emerging advanced transistors, representatively GAAFETs, are scaling down towards sub-3nm nodes. However, a multiscale simulation framework based on atomistic models and ab initio quantum simulation is still absent. Here, we propose such a simulation framework by fulfilling three challenging tasks, i.e., building atomistic all-around interfaces between semiconductor and amorphous gate-oxide, conducting large-scale first-principles calculations on the interface models containing up to 2796 atoms, and finally bridging the state-of-the-art atomic level calculation to commercial TCAD. With this framework, two unnoticed origins of interface states are demonstrated, and their tunability by changing channel size, orientation and geometry is confirmed. The quantitative study of interface states and their effects on device performance explains why the nanosheet channel is preferred in industry. We believe such a bottom-up framework is necessary and promising for the accurate simulation of emerging advanced transistors.