RIFO: Pushing the Efficiency of Programmable Packet Schedulers

TL;DR

RIFO is a resource-efficient programmable packet scheduler that maintains competitive performance with fewer memory resources, enabling scalable line-rate operation in data plane environments.

Contribution

The paper introduces RIFO, a novel packet scheduler that significantly reduces resource usage while achieving performance comparable to existing solutions.

Findings

RIFO reduces flow completion times by up to 4.91x in datamining workloads.

RIFO uses only three mutable memory cells and one FIFO queue per PIFO queue.

The implementation is scalable, simple (650 lines of P4 code), and runs at line rate.

Abstract

Packet scheduling is a fundamental networking task that recently received renewed attention in the context of programmable data planes. Programmable packet scheduling systems such as those based on Push-In First-Out (PIFO) abstraction enabled flexible scheduling policies, but are too resource-expensive for large-scale line rate operation. This prompted research into practical programmable schedulers (e.g., SP-PIFO, AIFO) approximating PIFO behavior on regular hardware. Yet, their scalability remains limited due to extensive number of memory operations. To address this, we design an effective yet resource-efficient packet scheduler, Range-In First-Out (RIFO), which uses only three mutable memory cells and one FIFO queue per PIFO queue. RIFO is based on multi-criteria decision-making principles and uses small guaranteed admission buffers. Our large-scale simulations in Netbench demonstrate that despite using fewer resources, RIFO generally achieves competitive flow completion times across all studied workloads, and is especially effective in workloads with a significant share of large flows, reducing flow completion time up to 4.91x in datamining workload compared to state-of-the-art solutions. Our prototype implementation using P4 on Tofino switches requires only 650 lines of code, is scalable, and runs at line rate.