When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA

TL;DR

This paper introduces a multi-exit Monte-Carlo Dropout Bayesian Neural Network framework optimized for FPGA deployment, significantly improving energy efficiency and calibration for safety-critical applications.

Contribution

It presents a novel multi-exit MCD-based BayesNN with a transformation framework for FPGA acceleration and optimization techniques for enhanced hardware performance.

Findings

Achieves higher energy efficiency than CPU, GPU, and state-of-the-art hardware.

Provides well-calibrated predictions with low algorithmic complexity.

Demonstrates effective FPGA-based acceleration for BayesNNs.

Abstract

Bayesian Neural Networks (BayesNNs) have demonstrated their capability of providing calibrated prediction for safety-critical applications such as medical imaging and autonomous driving. However, the high algorithmic complexity and the poor hardware performance of BayesNNs hinder their deployment in real-life applications. To bridge this gap, this paper proposes a novel multi-exit Monte-Carlo Dropout (MCD)-based BayesNN that achieves well-calibrated predictions with low algorithmic complexity. To further reduce the barrier to adopting BayesNNs, we propose a transformation framework that can generate FPGA-based accelerators for multi-exit MCD-based BayesNNs. Several novel optimization techniques are introduced to improve hardware performance. Our experiments demonstrate that our auto-generated accelerator achieves higher energy efficiency than CPU, GPU, and other state-of-the-art hardware implementations.