Instruction Set Architecture (ISA) for Processing-in-Memory DNN Accelerators

TL;DR

This paper presents a new instruction set architecture (ISA) designed for processing-in-memory (PIM) accelerators tailored for deep neural network inference, enabling unified development and compatibility across various hardware platforms.

Contribution

The paper introduces a universal ISA for PIM-based DNN accelerators that supports multiple device types and neural network models, facilitating unified toolchains and software stacks.

Findings

Implemented in open-source DNN compiler PIMCOMP-NN

Supported diverse PIM devices like RRAM, flash, FeFET, SRAM

Demonstrated compatibility with different hardware ISAs

Abstract

In this article, we introduce an instruction set architecture (ISA) for processing-in-memory (PIM) based deep neural network (DNN) accelerators. The proposed ISA is for DNN inference on PIM-based architectures. It is assumed that the weights have been trained and programmed into PIM-based DNN accelerators before inference, and they are fixed during inference. We do not restrict the devices of PIM-based DNN accelerators. Popular devices used to build PIM-based DNN accelerators include resistive random-access memory (RRAM), flash, ferroelectric field-effect transistor (FeFET), static random-access memory (SRAM), etc. The target DNNs include convolutional neural networks (CNNs) and multi-layer perceptrons (MLPs). The proposed ISA is transparent to both applications and hardware implementations. It enables to develop unified toolchains for PIM-based DNN accelerators and software stacks. For practical hardware that uses a different ISA, the generated instructions by unified toolchains can easily converted to the target ISA. The proposed ISA has been used in the open-source DNN compiler PIMCOMP-NN (https://github.com/sunxt99/PIMCOMP-NN) and the associated open-source simulator PIMSIM-NN (https://github.com/wangxy-2000/pimsim-nn).