SALSy: Security-Aware Layout Synthesis

TL;DR

SALSy introduces a security-aware layout synthesis methodology for integrated circuits, balancing security enhancements with power and performance trade-offs, validated through fabrication in 65nm CMOS technology.

Contribution

It presents the first comprehensive security closure approach integrating security metrics into layout synthesis with experimental validation.

Findings

Security metrics significantly improved with SALSy

Power increase remains modest

Validated on 65nm CMOS technology

Abstract

Integrated Circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of Hardware Trojans, can give an adversary access to privileged data and/or the means to corrupt the IC's internal computation. Post-fabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account and at the same time, this paper proposes a methodology for Security-Aware Layout Synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power-performance-area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the trade-offs between PPA and security are considered and a chip is fabricated in a 65nm CMOS commercial technology for validation purposes - a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power in order to achieve significantly improved security metrics.