Real-time FPGA Implementation of CNN-based Distributed Fiber Optic Vibration Event Recognition Method

TL;DR

This paper presents a fully on-chip, pipelined FPGA implementation of a CNN-based distributed fiber optic vibration event recognition system that achieves real-time processing with low power consumption without re-training.

Contribution

It introduces a novel hardware structure and network compression method to enable real-time, low-power FPGA deployment of CNN-based DVS algorithms without re-training.

Findings

Complete on-chip implementation with no accuracy loss

Real-time processing capability demonstrated

Low power consumption achieved

Abstract

Utilizing optical fibers to detect and pinpoint vibrations, Distributed Optical Fiber Vibration Sensing (DVS) technology provides real-time monitoring and surveillance of wide-reaching areas. This field has been leveraging Convolutional Neural Networks (CNN). Recently, a study has accomplished end-to-end vibration event recognition, enabling utilization of CNN-based DVS algorithms as real-time embedded system for edge computing in practical application situations. Considering the power consumption of central processing unit (CPU) and graphics processing unit (GPU), and the inflexibility of application-specific integrated circuit (ASIC), field-Programmable gate array (FPGA) is the optimal computing platform for the system. This paper proposes to compress pre-trained network and adopt a novel hardware structure, to design a fully on-chip, pipelined inference accelerator for CNN-based DVS algorithm, without fine tuning or re-training. This design allows for real-time processing with low power consumption and system requirement.An examination has been executed on an existing DVS algorithm based on a 40-layer CNN model comprising 2.7 million parameters. It is completely implemented on-chip, pipelined, with no reduction in accuracy.