The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic

TL;DR

This paper introduces QuickExact, an efficient and exact simulation algorithm for Silicon Dangling Bond (SiDB) logic, significantly reducing computation time for layout validation in emerging nanotechnology.

Contribution

The paper presents a novel algorithm with three techniques that drastically improves the speed of exact SiDB layout simulation compared to existing methods.

Findings

Runtime improved by over 5000x on random layouts

Runtime improved by over 2000x on established gate library

Demonstrates practical feasibility for SiDB layout validation

Abstract

The Silicon Dangling Bond (SiDB) logic platform, an emerging computational beyond-CMOS nanotechnology, is a promising competitor due to its ability to achieve integration density and clock speed values that are several orders of magnitude higher compared to current CMOS fabrication nodes. However, the exact physical simulation of SiDB layouts, which is an essential component of any design validation workflow, is computationally expensive. In this paper, we propose a novel algorithm called QuickExact, which aims to be both, efficient and exact. To this end, we are introducing three techniques, namely 1) Physically-informed Search Space Pruning, 2) Partial Solution Caching, and 3) Effective State Enumeration. Extensive experimental evaluations confirm that, compared to the state-of-the-art algorithm, the resulting approach leads to a paramount runtime advantage of more than a factor of 5000 on randomly generated layouts and more than a factor of 2000 on an established gate library.