Modeling Information Flow with a Multi-Stage Queuing Mode

TL;DR

This paper presents a nonlinear stochastic model for information flow in processors, capturing stage-based propagation and slowdown effects, with derived stationary distributions and validated approximations.

Contribution

It introduces a novel multi-stage queuing model with throttling, linking stochastic and deterministic descriptions of processor information flow.

Findings

Derived stationary distribution for the model

Developed a closure for the deterministic ODE system

Validated the approximation with numerical simulations

Abstract

In this paper, we introduce a nonlinear stochastic model to describe the propagation of information inside a computer processor. In this model, a computational task is divided into stages, and information can flow from one stage to another. The model is formulated as a spatially-extended, continuous-time Markov chain where space represents different stages. This model is equivalent to a spatially-extended version of the M/M/s queue. The main modeling feature is the throttling function which describes the processor slowdown when the amount of information falls below a certain threshold. We derive the stationary distribution for this stochastic model and develop a closure for a deterministic ODE system that approximates the evolution of the mean and variance of the stochastic model. We demonstrate the validity of the closure with numerical simulations.