Error Analysis of CORDIC Processor with FPGA Implementation

TL;DR

This paper presents a comprehensive error analysis of the CORDIC algorithm, focusing on angle approximation and quantization errors, and validates the analysis through FPGA implementation and simulation.

Contribution

It provides a detailed theoretical error analysis of CORDIC with FPGA implementation, including practical validation and comparison with floating-point models.

Findings

Theoretical error bounds are established for CORDIC.

FPGA implementation results align with theoretical error predictions.

Quantization and angle approximation are primary error sources.

Abstract

The coordinate rotation digital computer (CORDIC) is a shift-add based fast computing algorithm which has been found in many digital signal processing (DSP) applications. In this paper, a detailed error analysis based on mean square error criteria and its implementation on FPGA is presented. Two considered error sources are an angle approximation error and a quantization error due to finite word length in fixed-point number system. The error bound and variance are discussed in theory. The CORDIC algorithm is implemented on FPGA using the Xilinx Zynq-7000 development board called ZedBoard. Those results of theoretical error analysis are practically investigated by implementing it on actual FPGA board. In addition, Matlab is used to provide theoretical value as a baseline model by being set up in double-precision floating-point to compare it with the practical value of errors on FPGA implementation.