Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology

TL;DR

This paper analyzes UPMEM's commercial PIM technology using a new simulation framework, providing insights into its design and guiding future PIM architecture development for memory-intensive workloads.

Contribution

It introduces PIMulator, a flexible simulation framework, and offers a detailed characterization of UPMEM's PIM, highlighting key architectural features for future PIM designs.

Findings

PIMulator accurately models UPMEM's PIM performance.

Characterization reveals critical architectural features for future PIM.

Case studies identify design directions for future PIM architectures.

Abstract

Processing-in-memory (PIM) has been explored for decades by computer architects, yet it has never seen the light of day in real-world products due to their high design overheads and lack of a killer application. With the advent of critical memory-intensive workloads, several commercial PIM technologies have been introduced to the market ranging from domain-specific PIM architectures to more general-purpose PIM architectures. In this work, we deepdive into UPMEM's commercial PIM technology, a general-purpose PIM-enabled parallel architecture that is highly programmable. Our first key contribution is the development of a flexible simulation framework for PIM. The simulator we developed (aka PIMulator) enables the compilation of UPMEM-PIM source codes into its compiled machine-level instructions, which are subsequently consumed by our cycle-level performance simulator. Using PIMulator, we demystify UPMEM's PIM design through a detailed characterization study. Building on top of our characterization, we conduct a series of case studies to pathfind important architectural features that we deem will be critical for future PIM architectures to support